1. Field of the Invention
The present invention relates to an internal boosted voltage generator for a semiconductor memory device, and more particularly, to an active kicker for an internal boosted voltage generator.
2. Description of the Related Art
PNP type sense amplifiers have been used in conventional semiconductor memory devices. Recently, however, shared NP type sense amplifiers have been used to reduce chip size in semiconductor memory devices having high integration levels. Shared NP type sense amplifiers require a boosted voltage V.sub.pp for preventing data having a logic level of "1" from being lost during an active restore process due to the threshold voltage drop V.sub.t in an NMOS isolation transistor which isolates the bit line and the sense amplifier. Thus, an internal boosted voltage generator for generating the boosted voltage (hereinafter referred to as a "V.sub.pp generator") is required. The V.sub.pp generator is also used for word line drivers and a data output buffers, thereby improving the speed of the memory device.
The V.sub.pp generator is comprised of a main pump and an active kicker, wherein the main pump is for filling a V.sub.pp charge tank during a power-up state, and the active kicker, which is the subject of the present invention, is for supplementing the charge consumed during an active cycle.
FIG. 1 is a circuit diagram of a conventional active kicker. Referring to FIG. 1, the active kicker includes pumping means 10, precharging means 20 for precharging an output node N&lt;bst&gt; of the pumping means 10, and transferring means N3 for transferring the charge from the output node N&lt;bst&gt; to a node N&lt;V.sub.pp &gt;.
The pumping means 10 includes an inverter I2 and a capacitor C0 connected between an output node N&lt;pump&gt; of the inverter I2 and the output node N&lt;bst&gt; thereof. The input port of the inverter I2 is connected to an output node N&lt;1&gt; of an inverter I1 for inverting a control signal .phi.AKE.
The precharging means 20 includes an NMOS precharge transistor N2 having a source connected to the output node N&lt;bst&gt; of the pumping means 10 and a drain connected to a power supply voltage V.sub.cc, an NMOS transistor N1 having a source connected to a gate of the NMOS precharge transistor N2, that is, node N&lt;pre&gt;, and a gate and a drain both connected to the power supply voltage V.sub.cc. The precharging means 20 further includes a capacitor C2 that has one terminal connected to the node N&lt;pre&gt; and another terminal connected to the output node N&lt;1&gt; of the inverter I1. An internal power supply voltage IVC is used as the power supply voltage V.sub.cc, although an external power supply voltage may be used instead.
The transferring means N3 is comprised of an NMOS transistor having a drain connected to the output node N&lt;bst&gt; of the pumping means 10, a gate connected to a control signal .phi.TRAN and a source connected to the node N&lt;V.sub.pp &gt;.
In FIG. 1, C1, C.sub.pp and C.sub.cs represent parasitic capacitors. A switch is included for supplementing C.sub.cs by providing a consumed charge Q.sub.cs from the node N&lt;V.sub.pp &gt;.
FIG. 2 is an operational timing diagram of the active kicker shown in FIG. 1. Referring to FIG. 2, the operational principle of the conventional active kicker shown in FIG. 1 will be described. If the control signal .phi.AKE is initially in a logic "low" state, the node N&lt;1&gt; goes "high" to boost the node N&lt;pre&gt;, so that the node N&lt;bst&gt; is precharged to the level of the power supply voltage V.sub.cc. Then, if the control signal .phi.AKE is enabled to a "high" state, the precharge path is disabled, and the node N&lt;pump&gt; goes "high" so that the voltage of the node N&lt;bst&gt; is boosted to a predetermined level (hereinafter referred to as "V.sub.bst "). Then, the control signal .phi.TRAN is enabled to a "high" state to supplement the charge Q.sub.cs consumed during the active cycle through charge sharing between the node N&lt;bst&gt; and the node N&lt;V.sub.pp &gt;. The items induced based on the above concept can be expressed as follows. EQU V.sub.bst =V.sub.cc +V.sub.cc .times.C0/(C0+C1).apprxeq.2V.sub.cc( 1) EQU V.sub.pp =V.sub.cc .times.2C0/(C0+C.sub.cs) (2) EQU Q.sub.sp =C0.times.(V.sub.bst -V.sub.pp) or C.sub.pp .times.(V.sub.pp -V.sub.cs).apprxeq.C0.times.(2V.sub.cc -V.sub.pp) (3) EQU Q.sub.cs =V.sub.pp .times.(C.sub.pp .times.C.sub.cs)/(C.sub.pp +C.sub.cs)-V.sub.cc .times.C.sub.cs /2.apprxeq.C.sub.cs .times.(V.sub.pp -V.sub.cc /2) (4)
wherein V.sub.bst represents the voltage level of the node N&lt;bst&gt;, V.sub.pp represents the voltage level of the node N&lt;V.sub.pp &gt;, Q.sub.sp represents supplied charge, and Q.sub.cs represents consumed charge, respectively.
Hereinafter, problems associated with the conventional active kicker shown in FIG. 1 will be described with reference to FIGS. 3 and 4.
FIG. 3 is a clamp curve of IVC and V.sub.pp with respect to the external power supply voltage EV.sub.cc. IVC represents the output voltage of an internal voltage converter, that is, an internal power supply voltage, and V.sub.pp, as a boosted voltage, represents the voltage of the node N&lt;V.sub.pp &gt; shown in FIG. 1. For comparison, FIG. 1 also shows V.sub.pp ' which represents the voltage of the node N&lt;V.sub.pp &gt; of an active kicker in accordance with the present invention which is described below with reference to of FIG. 5. However, for purposes of explaining the problems associated with the conventional active kicker, the following discussion will only refer to the signals associated with the circuit shown in FIG. 1.
Generally, the difference between IVC and V.sub.pp is optimally set to about 2.5 V which is lower than the target operational voltage of 3.0 V for low V.sub.cc margin. Assuming that the optimal difference between V.sub.pp and IVC is .DELTA.0 when IVC is increased from 2.5 V to 3.0 V, the difference A between the changed V.sub.pp and IVC (referred to as .DELTA.1) can be expressed as follows, based on the above-referenced formula (2): EQU V.sub.pp (3.0 V)-V.sub.pp (2.5 V)=2C0/(C0+C.sub.cs).times..DELTA.V.sub.cc .apprxeq.1.6.times..DELTA.V.sub.cc ( 5) EQU .DELTA.1-.DELTA.0=2C0/(C0+C.sub.cs)-1!.times..DELTA.V.sub.cc .apprxeq.0.6.times..DELTA.V.sub.cc ( 6)
As shown from the above formulas, since the change in V.sub.pp is greater than that of V.sub.cc, that is, IVC, e.g., greater than about 1.6 times .DELTA.V.sub.cc, V.sub.pp is greatly increased when IVC is necessarily increased to 5 V or higher as required in the case where a burn-in-mode for testing the reliability of the semiconductor memory device is required. As a result, severe stress applied to the device. In addition, the large amount of charge required to increase V.sub.pp results in excessive current consumption.
FIG. 4 is a conceptual curve of the supplied charge Q.sub.sp and the consumed charge Q.sub.cs according to the change in V.sub.pp. Solid lines are for the conventional active kicker shown in FIG. 1. For comparison, dashed lines illustrate the operation of an active kicker in accordance with the present invention which is described below with reference to of FIG. 5. However, for purposes of explaining the problems associated with the conventional active kicker, the following discussion will only refer to the curves associated with the circuit shown in FIG. 1.
Referring to FIG. 4, in view of the active kicker, it is desirable that Q.sub.sp and Q.sub.cs have the same value so that the X-axis value of a point where two curves intersect with each other is at an optimum V.sub.pp. The above-described problems of the conventional active kicker are apparent from FIG. 4, that is, as V.sub.cc increases, the optimum V.sub.pp is greatly increased.